The present invention relates in general to analog multiplier/divider circuits, and more particularly those utilizing the logarithmic V-I characteristic of substrate bipolar transistors easily fabricated in standard CMOS processes.
The use of the highly predictable logarithmic-antilogarithmic properties of bipolar diodes and transistors to form analog computational circuits which perform multiplication, division, exponents, and other mathematical functions is well known in the field of analog electronics. An excellent summary of such techniques can be found in "The Non-Linear Circuits Handbook" published by Analog Devices, 1974. These techniques are also the basis of numerous issued patents including:
G. E. Platzer, U.S. Pat. No. 3,152,250, issued Oct. 6, 1964 PA0 D. E. Blackmer, U.S. Pat. No. 3,714,462, issued Jan. 30, 1973 PA0 H. K. Henson, U.S. Pat. No. 3,805,092, issued Apr. 16, 1974 PA0 D. R. Curtis, U.S. Pat. No. 4,004,141, issued Jan. 18, 1977
Most of the teachings of the patents in the prior art are well suited to being embodied in a single monolithic integrated circuit utilizing standard bipolar processes, as demonstrated by the numerous commercially available analog computation integrated circuit products (ICs) such as the AD536, AD538, AD636, and AD637 manufactured by Analog Devices, Inc., and others.
In recent years CMOS processes which allow the fabrication of MOS transistors on a single substrate have emerged as a dominant technology especially for digital logic circuits, because of its generally higher density and lower power consumption than that obtainable with bipolar IC processes. CMOS processes are also well suited for implementing analog circuits, making them popular for integrating large electronic systems containing both digital logic and analog functions into a single piece of semiconductor material, a feature not practical with bipolar processes. Much research has been done recently to implement analog computational circuits utilizing MOS transistors instead of bipolar transistors to allow the inclusion of such circuits in integrated CMOS digital/analog systems, and several patents have been issued disclosing several of these techniques, including: U.S. Pat. No. 3,956,643, U.S. Pat. No. 4,906,873, and U.S. Pat. No. 4,978,873.
Although such CMOS implementations have been successful, the resulting computational circuits still do not provide the dynamic range or accuracy obtainable from their bipolar counterparts. Moreover, in most circuit configurations utilizing bipolar transistors, device mismatches generally produce only a gain or scale factor error. Such errors are easily trimmed out or adjusted for elsewhere in the system in bipolar applications. In MOS configurations, device mismatches generally produce both linearity and gain errors, the former being much more difficult to correct or accommodate.
Hence, implementing analog computational circuits with bipolar transistors in most cases is still preferred. The preference accounts for the occurrence of many two-IC solutions found in the market, an example of which is digital multimeters capable of measuring the RMS value of an AC voltage. One IC is fabricated in a CMOS process and contains all of the digital circuits and majority of analog circuits; the other IC, fabricated in a bipolar process, contains an analog multiplier/divider configured as an RMS-to-DC converter. It would be highly desirable to integrate the RMS-to-DC converter with the remaining voltmeter circuitry into a single IC without suffering reduced RMS conversion performance.
Two possible solutions remain. One possible solution is to utilize a more advanced process, generally called BiCMOS, which allows the fabrication of both isolated bipolar transistors and MOS transistors on a single substrate. However, such processes presently can require nearly twice as many processing steps or more than a standard CMOS process, resulting in a significantly higher cost to manufacture an IC fabricated by such a process.
The other possible solution entails utilizing the substrate bipolar parasitic transistor inherent in even the simplest of CMOS processes. Such a transistor is considered parasitic because it is not intentionally fabricated, but instead results as a normally undesirable component of the fabricated MOS transistor.
An important characteristic of these parasitic bipolar transistors is that their collectors and the substrate are one and the same. That is, the collectors are all common, and the currents flowing through one collector cannot be distinguished from the current flowing through the collector of another transistor fabricated on the same piece of semiconductor material. All such collector currents are summed internal to the substrate and appear in combination at any electrode connected anywhere to the substrate. Hence, these parasitic transistors are also referred to as substrate bipolar transistors, and have very limited applications.
In particular, they may not be used in any of the computational circuits found in the prior art. In all applications using prior art circuits at least one and typically all collectors must be separate and independent of each other. This separation is required because in all prior art circuits, the collector is the primary electrode which is monitored by the circuitry either for the purpose of forcing the collector currents to substantially equal an input signal, or for the purpose of extracting the desired output signal. Thus, none of the prior art circuit topologies may be employed when the collectors of all bipolar transistors are in common, as is the case for the substrate bipolar available in standard CMOS processes.